This invention relates to a capacitor-array D/A converter including a capacitor array and, in particular, to a capacitor arrangement for use in the capacitor array of the capacitor-array D/A converter.
An existing D/A (digital-to-analog) converter is used in various kinds of electronic circuits to convert a digital signal into a corresponding analog signal. With an improvement in performance of the electronic circuits, the D/A converter is required to have high accuracy.
For example, U.S. Pat. Nos. 5,949,362 and 6,236,346 disclose techniques for increasing the accuracy of the D/A converter, i.e., techniques for improving the linearity of a conversion characteristic upon conversion from a digital code into an analog voltage.
Referring to FIG. 1, description will be made of a current cell arrangement of a D/A converter disclosed in U.S. Pat. No. 5,949,362 as a first conventional technique for improving the linearity. A current cell matrix 25 comprises a first array 31 of a plurality of current source cells 32 positioned to the right of a dashed line 33. The cells of the first array 31 extend in first and second directions perpendicular to each other. The current cell matrix 25 is provided with two-dimensional symmetrical control means 35 for operating predetermined current source cells of the first array 31 based upon at least a portion of digital input words and in a symmetrical sequence in both the first and the second directions with respect to a medial position of the first array. The medial position defines a centroid for the first array as shown by an imaginary point 39. As an increasing number of current sources are switched, the current source cells labeled 1-31 are sequentially operated. Accordingly, the D/A converter illustrated in FIG. 1 is less susceptible to variations in threshold voltage and current factor as may otherwise be caused by process gradients.
The first array 31 further comprises a plurality of second current source cells or LSB cells 32a labeled D0 through D4 in FIG. 1. The two-dimensional symmetrical control means 35 further comprises LSB cell control means for operating the LSB current source cells 32a based upon predetermined least significant bits (LSBs) of the digital input words. The LSB current source cells (D1-D4) are positioned in a medial portion of the first array to reduce the influence of process gradients. The D/A converter 25 includes a second array 38 substantially similar to the first array 31 and located adjacent the first array 31. The two-dimensional symmetrical control means 35 includes geometrical averaging means for operating the current source cells 32 in the first and second arrays 31 and 38 in pairs and in a substantially true mirror image sequence. For example, both cells of a pair may be connected to the same control signal and the output of each cell is half the desired combined output current.
Referring to FIG. 2, description will be made of a capacitor arrangement of a D/A converter which is disclosed in U.S. Pat. No. 6,236,346 as a second conventional technique for improving the linearity. Respective capacitance elements C are included in different cells 44 of a cell array 42. The cells 44 have switch circuits 46-1 to 46-16, respectively. Each switch circuit 46 has an input node connected to an output node (denoted by xe2x80x9cXxe2x80x9d in FIG. 2) of a corresponding one of the cells 44. The output node is connected to a bottom plate of the capacitance element C in the cell. Each switch circuit 46 has three terminals, i.e., first through third terminals. The first terminals of the switch circuits 46 are connected in common to receive an input voltage VIN. The second terminals are connected in common to receive a negative reference voltage VSS. The third terminals are connected in common to receive a predetermined reference potential VREF. Each switch circuit 46 is controllable, in response to a selection signal S supplied thereto, to connect the input node to one of the first, the second, and the third terminals. The capacitance elements C in the different cells have top plates connected in common as an output VTOP of the D/A converter.
Referring to FIG. 3, five binary-weighted capacitors C0 to C4 are provided by the capacitance elements C in the different cells. The capacitor C0 is provided by the capacitance element C of the cell 1 alone. The capacitor C1 is provided by the capacitance element C of the cell 2 alone. The capacitor C2 is provided by the capacitance elements C of the cells 3 and 4 connected in parallel. The capacitor C3 is provided by the capacitance elements C of the cells 5 to 8 connected in parallel. The capacitor C4 is provided by the capacitance elements C of the cells 9 to 16 connected in parallel. Therefore, the capacitance ratio of the capacitors C0 to C4 is 1:1:2:4:8.
For each row, each column, and each diagonal of the cell array 42, the sum of respective selection-sequence positions of the cells is the same (34 in this case). Referring to FIG. 4, a table shows an x-error and a y-error for each ordinal position in the selection sequence of the cells. For those cells that are selected in response to a given input code, the x-errors are summed to produce a total x-error xcexa3x and the y-errors are summed to produce a total y-error xcexa3y. By arranging the cell array in the configuration of a magic square as illustrated in FIG. 2, it is possible to realize a high-accuracy cell array circuit capable of two-dimensionally canceling an accumulation of graded and symmetrical errors in different rows and columns and to realize a high-accuracy D/A converter.
However, if the first conventional technique is similarly applied to a capacitor-array D/A converter or in case of the capacitor-array D/A converter according to the second conventional technique, the following disadvantages will arise.
As a first problem, the linearity of the D/A converter is deteriorated under the effect of a parasitic capacitance.
The reason is as follows. An output voltage of the D/A converter of a current cell matrix type according to the first conventional technique is determined exclusively by current values of the respective current source cells. On the other hand, an output voltage of the capacitor-array D/A converter is determined by capacitive voltage division from the sum of (1) capacitance values of the respective array capacitors, (2) capacitance values of coupling capacitors produced between the capacitors and connection lines for connecting the array capacitors and the switches, and (3) capacitance values of coupling capacitors produced between the array capacitors and connection lines for connecting the array capacitors to one another. In the first conventional technique, control is carried out by means of a mirror image (or symmetrical) arrangement and a mirror image (or symmetrical) sequence. Under such control, however, no more than the influence of variation in production accuracy of the current source cells is suppressed. Rather, the complexity in arrangement and control results in a complicated layout of the connection lines for transmission of control signals. Therefore, complicated coupling occurs between the array capacitors and the connection lines for connecting the array capacitors and the switches and between the array capacitors and the connection lines for connecting the array capacitors to one another. As a result, the linearity of the output voltage is degraded. In the second conventional technique, the capacitor cells are arranged in the configuration of the magic square. In this case also, no more than the influence of variation in production accuracy of capacitor cells is suppressed and the complexity in arrangement results in a complicated layout of the connection lines for the control signals. The linearity is deteriorated under the effect of the coupling capacitors in the similar manner as mentioned in conjunction with the first conventional technique.
A second problem is an increase in circuit scale.
This is because the array is divided into upper and lower rows in order to realize the mirror image arrangement. The mirror image arrangement as in the first conventional technique can not be realized by a single-row array. If the array divided into the upper and the lower rows is controlled by the control circuit located on one side of the array, a control signal for a switch corresponding to another capacitor on the other side passes over a capacitor on the one side. In this event, the linearity is deteriorated under the influence of coupling between the array capacitor and the control signal for the switch corresponding to another array capacitor. In order to prevent the control signal for the switch corresponding to another array capacitor from passing over the array capacitor, control circuits must be arranged at least on two sides, i.e., upper and lower sides. In this case, since the control circuits are separately arranged and supplied with signals from a single common decoder, a wide space is required for connection lines for transmission of the control signals. Furthermore, in order to realize the mirror image sequence, two similar arrays are provided. As a result, an array area, the number of control circuits, and the number of control signals are doubled.
It is an object of this invention to provide a capacitor-array D/A converter and a capacitor array for the capacitor-array D/A converter which are capable of solving the above-mentioned problems.
Capacitor-array D/A converters according to this invention are as follows:
(1) A capacitor-array D/A converter which comprises:
a thermometer decoder (103) for thermometer-decoding a decoder input signal having first through m-th input bits (D3 to D7) to produce an output signal (107) having first through n-th output bits (T1 to T31), where m is an integer not less than two and where n is equal to (2mxe2x88x921);
first through n-th switches (SU1 to SU31) corresponding to the first through the n-th output bits of the thermometer decoder; and
a capacitor array (104) comprising first through n-th capacitors (8C1 through 8C31) corresponding to the first through the n-th switches;
each of the first through the n-th switches being supplied with a corresponding bit of the first through the n-th output bits from the thermometer decoder, the corresponding bit corresponding to the each of the first through the n-th switches, each of the first through the n-th switches operating so that, when the corresponding bit has a logic xe2x80x9c1xe2x80x9d level, a corresponding capacitor of the first through the n-th capacitors is applied with a predetermined voltage (VREF) not equal to zero and that, when the corresponding bit has a logic xe2x80x9c0xe2x80x9d level, the corresponding capacitor is grounded (205), the corresponding capacitor corresponding to the each of the first through the n-th switches;
the capacitor array having a main area;
the first through the n-th capacitors being arranged in the main area and in a row direction of the capacitor array consecutively from the center outward to the left and the right to be symmetrical.
(2) A capacitor-array D/A converter as described in (1), wherein:
the first and the m-th input bits of the decoder input signal of the thermometer decoder are a least significant bit and a most significant bit of the decoder input signal, respectively;
the first and the n-th output bits of the output signal of the thermometer decoder being a least significant bit and a most significant bit of the output signal, respectively.
(3) A capacitor-array D/A converter as described in (1), further comprising first through n-th connection lines (312) corresponding to the first through the n-th switches;
each of the first through the n-th switches operating so that, when the corresponding bit has a logic xe2x80x9c1xe2x80x9d level, the corresponding capacitor is applied with the predetermined voltage through a corresponding connection line of the first through the n-th connection lines and that, when the corresponding bit has a logic xe2x80x9c0xe2x80x9d level, the corresponding capacitor is grounded through the corresponding connection line, the corresponding connection line corresponding to the each of the first through the n-th switches.
(4) A capacitor-array D/A converter as described in (3), the capacitor array having an additional area adjacent to the main area in a column direction which is perpendicular to the row direction, wherein:
the first through the n-th switches are arranged in the adjacent area of the capacitor array and in the row direction consecutively from the center outward to the left and the right to be symmetrical;
the first through the n-th connection lines extending in the column direction without intersecting with one another.
(5) A capacitor-array D/A converter as described in (4), wherein:
the capacitor array further comprises dummy capacitors (8CD1, 8CD2) each of which does not correspond to any one of the first through the n-th switches and is permanently connected to the ground, the dummy capacitors being arranged in the main area at both sides of the first through the n-th capacitors.
Capacitor arrays according to this invention are as follows:
(6) A capacitor array (104) for use in a capacitor-array D/A converter which comprises:
a thermometer decoder (103) for thermometer-decoding a decoder input signal having first through m-th input bits (D3 to D7) to produce an output signal (107) having first through n-th output bits (T1 to T31), where m is an integer not less than two and where n is equal to (2mxe2x88x921);
first through n-th switches (SU1 to SU31) corresponding to the first through the n-th output bits of the thermometer decoder; and
the capacitor array comprising first through n-th capacitors (8C1 through 8C31) corresponding to the first through the n-th switches;
each of the first through the n-th switches being supplied with a corresponding bit of the first through the n-th output bits from the thermometer decoder, the corresponding bit corresponding to the each of the first through the n-th switches, each of the first through the n-th switches operating so that, when the corresponding bit has a logic xe2x80x9c1xe2x80x9d level, a corresponding capacitor of the first through the n-th capacitors is applied with a predetermined voltage (VREF) not equal to zero and that, when the corresponding bit has a logic xe2x80x9c0xe2x80x9d level, the corresponding capacitor is grounded (205), the corresponding capacitor corresponding to the each of the first through the n-th switches;
the capacitor array having a main area; wherein:
the first through the n-th capacitors are arranged in the main area and in a row direction of the capacitor array consecutively from the center outward to the left and the right to be symmetrical.
(7) A capacitor array as described in (6), wherein:
the first and the m-th input bits of the decoder input signal of the thermometer decoder are a least significant bit and a most significant bit of the decoder input signal, respectively;
the first and the n-th output bits of the output signal of the thermometer decoder being a least significant bit and a most significant bit of the output signal, respectively.